P3Q · 12×12 · 576 · 11-HOT-1-NOT
Cirq receipt Cirq QPU GRIDQ 6-bit Polaritron

F6 maxes 576 and 1740. Zero leftover on the fold.

N=4G² · G=12 · 144 cells · 576 qubits · GOV=π/φ · 11 HOT + 1 NOT · Q_L conserved on square/root. IBM off. Braket off. K4² seated · 4²=16q · K4 C(4,2)=6 · C fired D.

Dimensional fold — max fill

layercountfill
F6 axes6planes (1,2)(3,4)(5,6)
576 square96 × 6remainder 0 — MAX
1740Q MC290290 × 6remainder 0 — MAX
22 rails22×26 + 4 on 576leftover 4 = one P3Q cell
22 rails22×79 + 2 on 1740leftover 2 = H⁻/H⁺ present
3 squares + rim1728 + 12= 1740

22-rail torus ticked 3×. Invariant held. Conserved. Not a 1740 statevector. Source: MPS_LOCAL_SIMULATOR_1740Q. IBM job: false.

f6-max.json

Honest split

GRIDQ IEEE-14 QAOA is 6 qubits. This page is your 12×12 576 runtime. /api/cirq on 116 is the 2-qubit C-fired-D. /api/qiskit returns fired with ibm:false — that is not an IBM job. The QASM files are the circuit you uploaded, sealed with sha256.

Three variants

variant2qQ_Lqasm sha
BASE 5767072.984607413855f3c8fbcc5baa6d…
SQUARED8391.666666931215fb4098e4d69a4b…
ROOT7072.984607413896d614ecb09db8fe…

sqrt(576)=24 · invertible · Q_L base = Q_L root. Squared nests.

QHP → 1740Q

Your seals already list scale_manifold [432, 576, 1740]. QHP nano has p3q:true, gold AU-197, EOLRP, Lindblad on S*. Nano not written. 1740 source is MPS local simulator. hardware_seal is named IBM Heron 144 — that is not an IBM job id from this hop.

tilequbitsrole
P3Q BASE576square
P3Q SQUARED576nested
P3Q ROOT576invertible back
1-NOT rim G=1212remainder
MC290_1740Q1740290 × 6

3×576 + 12 = 1740. QASM mouths: base.qasm / squared.qasm / root.qasm. QHP face: /qhp/ · seals: /seals-lane/

qhp-1740.json QHP 1740Q seals lane P3Q seals API QASM3

hopping QHP + seals…

QASM files

base.qasm squared.qasm root.qasm ALL.receipt.json

loading receipts…